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@article{Lin2024ModelingAS, title={Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development}, author={Xi-Wei Lin and Salvatore M. Amoroso and Ko-Hsin Lee and Meng Hsuan Ke and Tue Gunst and Pavel Tikhomirov and Plamen Asenov}, journal={2024 IEEE International Memory Workshop (IMW)}, year={2024}, pages={1-4}, url={https://api.semanticscholar.org/CorpusID:269988847}}
  • Xi-Wei Lin, Salvatore M. Amoroso, P. Asenov
  • Published in International Memory Workshop 12 May 2024
  • Engineering, Computer Science, Physics

Examples are given to demonstrate the value of multiscale, multi-physics modeling of complex problems, including a) row hammer and 4F2 floating body effects in DRAM; b) RTN and program noise in 3D NAND; c) 3D unit process, integration, and wafer warpage.

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20 References

Investigation of Program Noise in Charge Trap Based 3D NAND Flash Memory

The mechanisms and characteristics of program noise (PN) in charge trap based 3D NAND flash memory are investigated in this work. Electron injection statistics is found to be primarily responsible

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    J. HanS. Park J.M. Park

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    2023 IEEE Symposium on VLSI Technology and…

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For the past decades, the density of DRAM has been remarkably increased by making access transistors and capacitors smaller in size per unit area. However, shrinking devices far beyond the 10 nm

  • 4
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  • 9
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The transition from planar (2D) to three-dimensional (3D) arrays represented a turning point for the phenomenology of random telegraph noise (RTN) in NAND Flash technologies. The relevant changes in

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As an important constraint on the threshold voltage (Vt) distribution, the random telegraph noise (RTN) has attracted much attention due to the widely used multi-bit-per-cell technology in 3D NAND

  • 6
First Theoretical Modeling of the Bandgap-Engineered Oxynitride Tunneling Dielectric for 3D Flash Memory Devices Starting from the Ab Initio Calculation of the Band Diagram to Understand the Programming, Erasing and Reliability
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Bandgap engineered (BE) tunneling barrier using oxynitride (SiON) is a key enablement of charge-trapping devices adopted in commercial 3D Flash memories. For the first time we use the ab initio

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